IJRE – Volume 3 Issue 3 Paper 3


Author’s Name : Divya Prabha.A | Murali Dharan.V |  Varatharaj.M

Volume 03 Issue 01  Year 2016  ISSN No:  2349-252X  Page no: 11-13






In all signal processing applications the main problem faced by the processor is its propagation delay. It makes the process to be tedious. Conventionally The Binary signed numbers(BSD) were used to overcome this problem,(BSD’s) are known for its carry free addition and borrow free subtraction, but the addition process is more complicated when the number of bits is increased. Some of main problems in BCD’s are they provide less storage density and large complexity. The main aim of this project is to design a efficient adder that solves the above problems with the use of Quaternary signed digit number system. The Quaternary signed digit number provides carry free addition with high storage capacity.QSD is represented by a number from -3 to +3.Carry free addition of higher bit numbers with constant delay and less complexity is possible by QSD number system. So that the speed of the processor is increased. It is simulated by using Xilinx tool 14.1 ISE.


Signed digit number system, Binary signed digit number system, Quaternary signed digit number system.


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