IJRE – Volume 4 Issue 1 Paper 1


Author’s Name :  Suganya S | Latha P | Naveenkumar R | Abiramasundari S

Volume 04 Issue 01  Year 2017  ISSN No:  2349-252X  Page no: 1-5






The propounded work brings a new parallel FIR filter structures beneficial to symmetric coefficients in terms of the hardware cost, under the situation that the taps in the filter structure is a multiple of 2 or 3. The propounded parallel FIR structures exploits the inherency of symmetric coefficients breaking down the number of multipliers in sub-filter section at the expense of additional adders in the processing blocks to half the number. Upon interchanging multipliers with adders is recommended because adders weigh less on comparing to multipliers in terms of silicon area; in addition the aloft from the additional adders in pre processing and post processing blocks remains unmoved and do not increase along with the length of the FIR filter, whereas the number of reduced multipliers enlarges along with the length of the FIR filter. For example, in a four-parallel 72-tap filter, the propounded structure rescues 27 multipliers at the expenditure of 11 adders. On considering for a four-parallel 576-tap filter, the proposed structure rescues 216 multipliers at the outlay of 11 adders. On the whole, the proposed parallel FIR structures leads to significant hardware reduction for symmetric convolutions from the current FFA parallel FIR filter, especially when the length of the filter is large.


Digital Signal Processing (DSP), Fast finite-Impulse Response (FIR) Algorithms (FFAs), Co-ordinate FIR, Symmetric-Convolution, Very Large Scale Integration (VLSI)


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