IJRE – Volume 4 Issue 1 Paper 2


Author’s Name :  Latha P | Suganya S | Naveenkumar R | Arivoli S

Volume 04 Issue 01  Year 2017  ISSN No:  2349-252X  Page no: 6-9






As the aspect ratio of the devices shrinks down, the power supply voltage should be shortened to meet low power requirements, and the threshold voltage should also be reduced to achieve high performance. This however leads to aggressive increase in leakage current; hence the circuit’s reliability is also affected. A new domino circuit is suggested with reduced power and lower leakage for wide fan-in gates. The main intention was to make domino circuits more potent and with lower leakage and without dramatic speed degradation. The technique employed in this paper is that, the pull-up network’s mirrored current is compared with its worst case leakage current and it downturns the upper and lower boundary of the voltage swing on the dynamic node. The parasitic capacitance on the dynamic node and the keeper size for very large fan-in gates is also decreased by the expected circuit and hence the circuit can be used as a small keeper for wide fan-in gates to implement fast and robust circuits. The footer transistor is also used to shorten the leakage current. Simulation results of wide fan-in gates are build using Tanner in 16-nm technology.


Domino logic,Leakage-tolerant, Voltage Swing, Wide fan-in


  1. Alioto, M Palumbo, G. & Pennisi, M (2010) “Understanding the effect of process variations on the delay of static and domino logic,” IEEE Trans. Very Large Scale (VLSI) Syst., vol. 18, no. 5, pp. 697–710.
  2. Bowman. K, Duval. S. G, and Meindl . J. D (Feb. 2002)  “Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration,” IEEE J. Solid-State Circuits,vol. 37, no. 2, pp. 183–190.
  3. Dadgour. H. F and Banerjee. K (Nov. 2010) “A novel variation-tolerant keeper architecture for high-performance low-power wide fan-in dynamic or gates,” IEEE Trans. Very Large Scale (VLSI) Syst., vol. 18, no. 11, pp. 1567–1577.
  4. Kim, CH. K. Roy, Hsu, S. Krishnamurthy, v & Borkar, v (2006) “A process variation compensating technique with an on-die leakage current sensor for nanometre scale dynamic circuits,” IEEE Trans. Very Large Scale (VLSI) Syst., vol. 14, no. 6, pp. 646–64.
  5. Lih, Y. Tzartzanis, N. & Walker, WW. (2007) “A leakage current replica keeper for dynamic circuits,” IEEE J. Solid-State Circuits, vol. 42, no. 1, pp.48-55.
  6. Mustafa, V. Anis, M. & Elmasry, M. (2011) “Novel timing yield improvement circuits for high-performance low-power wide fan-in dynamic OR gates,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 10, pp. 1785–1797.
  7. Peiravi. A and Asyaei. M (2012) “Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates, integration,” VLSI J., vol. 45, no. 1, pp. 22–32.
  8. Peiravi. A and Asyaei. M (May 2013) “Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, NO. 5.
  9. Rabaey. J. M, Chandrakasan . A, and Nicolic. B, Digital Integrated Circuits: A Design Perspective, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 2003.
  10. Roy, K. Mukhopadhyay, S. & Mahmoodi-Meimand, H. (2003) “Leakage current mechanisms and leakage reduction techniques in deepsubmicrometer CMOS circuits,” Proc. IEEE, vol. 91, no. 2, pp. 305–327.
  11. Shan hag, N. Soumyanath, K. & Martin, S. (2000) “Reliable low-power design in the presence of deep submicron noise,” in Proc. ISLPED, pp. 295-302.
  12. Tarun Kumar Gupta, Kavita Khare (February 8, 2013) “A New Technique for Leakage Reduction in 65 nm Footerless Domino Circuits,” Circuits and Systems, 4, 209-216.
  13. Volkan Kursun and Eby G. Friedman (Apr. 2002) “Low Swing Dual Threshold Voltage Domino Logic,”ACM/SIGDA Great Lakes Symposium on VLSI; pp. 47-52.
  14. Wang. L, Krishnamurthy. R, Soumyanath. K and Shanbhag. N (2000) “An energy-efficient leakage-tolerant dynamic circuit technique,” in Proc. Int.ASIC/SoC Conf., pp. 221–225.