IJRE – Volume 4 Issue 2 Paper 5


Author’s Name :  Mohan R | Vinitha K V

Volume 04 Issue 02  Year 2017  ISSN No:  2349-252X  Page no: 20-24






A leakage current compensation design for nano scale SRAMs is proposed in this paper. The proposed SRAMs cell is implemented with transmission gate.  The proposed compensation design is composed of a leakage current sensor and compensation circuit. The leakage current sensor, which generates a warning signal if the leakage is over a predefined threshold, and a compensation circuit following the sensor, which will be activated to speed up the read operation. It is used to enhance the write ability of the SRAM cell using transmission gates and further modification is done in the write assist circuit to reduce the power consumption and delay. The proposed circuit gives better result. The proposed Static Random-Access Memory is implemented using the TSMC 40-nm (CMOS) Complementary Metal Oxide Semiconductor logic technology. The energy per access is measured to be 0.9411 pJ given a 600-mV power supply and a 54-MHz system clock rate. The reduce power delay 2.58 ns and 27.86% of the average power dissipation reduced.

Key Words:

Compensation circuit, disturb free, leakage current sensor, single-ended Static Random-Access Memory cell, SRAM


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