IJRE – Volume 4 Issue 3 Paper 6


Author’s Name :  Dr K G Parthiban | V S Vidhyakumari

Volume 04 Issue 03  Year 2017  ISSN No:  2349-252X  Page no: 20-23






This project presents the design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial points. Those techniques are robust to any variations in the ECG signal with high sensitivity and precision. Two databases of the heart signal recordings from the MIT PhysioNet and the American Heart Association were used as a validation set to evaluate the performance of the processor. Based on application-specified integrated circuit (ASIC) simulation results, the overall classification accuracy was found to be 86% on the out-of-sample validation data with 3-s window size. The architecture of the proposed ESP was implemented using 65-nm CMOS process. It occupied 0.112-mm2 area and consumed 2.78-µW power at an operating frequency of 10 kHz and from an operating voltage of 1 V. It is worth mentioning that the proposed ESP is the first ASIC implementation of an ECG-based processor that is used for the prediction of ventricular arrhythmia up to 3 h before the onset.

Key Words:

Adaptive Techniques, Application-Specified Integrated Circuit (ASIC), Classification, Electrocardiograph (ECG), Feature Extraction, Low Power, Ventricular Arrhythmia


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