IJRE – Volume 4 Issue 4 Paper 2


Author’s Name :  M Anitha Pakiyaraj | K Priyanga

Volume 04 Issue 04  Year 2017  ISSN No:  2349-252X  Page no: 7-12






Low power circuit designs have been an important issue VLSI design areas. Multipliers play a major role in high performance systems. Vedic mathematics is world renowned for its algorithms that yield quicker results, be it for mental calculations or hardware design. The Urdhva-Tiryagbhyam Vedic multiplier is one such multiplier which is effective both in terms of speed and power. Adiabatic logic style is said to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and some of energy stored at load capacitance can be recycled instead of dissipated as heat. Compare with other multiplier the Vedic multiplier consume very less power, here combining with this adiabatic logic the power consumption is dramatically reduced. In analysis, 2PASCL (Two Phase Adiabatic Static Clock Logic) logic is compared with two logic families, ECRL (Efficient Charge Recovery Logic) and PFAL (Positive Feedback Adiabatic Logic) for Vedic multiplier circuits. In our project we use the 2PASCL adiabatic logic instead of CMOS logic for the design of Vedic multiplier to reduce the power consumption. By using the Xilinx ISE simulator the simulation has been executed. And for the hardware implementation Spartan 3E FPGA is used.

Key Words:

Adiabatic logic, 2 Phase Adiabatic Static Clock Logic (2PASCL), Vedic multiplier, Low power


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