IJRE – Volume 5 Issue 2 Paper 5


Author’s Name :  Mr Chandra Shekar P | Mrs Shalini V S

Volume 05 Issue 02  Year 2018  ISSN No:  2349-252X  Page no: 14-17






In the modern world one of the biggest challenges is to reduce the power consumption in electronic devices which will lead to longer battery life while maintaining high performance. Reduction of power consumption can be done by low power design. This can be achieved by adiabatic logic technique. In this paper, conventional CMOS circuits and ECRL circuits for flip flop for SR, JK, D& T are designed using Cadence Virtuoso Tool at 45nm process technology &Stimulated using Spectre. Power consumption of CMOS & ECRL flip flop is compared and computed.


Adiabatic, CMOS, Power Analysis, ECRL, Flip Flop, 45nm Technology


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