CLOCK POWER MITIGATION OF MULTI-BIT FLIP-FLOPS USING MERGING TECHNIQUE
Author’s Name : T Bhuvaneswari | C Prema
Volume 05 Issue 04 Year 2018 ISSN No: 2349-252X Page no: 4 – 8
In modern VLSI design power has been become a burning issue. Reducing power consumption in design it enables better and cheaper products to be designed and power-related chip failures to be minimized. The power consumed by clocking gradually takes a dominant part. Multi-bit flip-flop is an effective method for clock power consumption reduction. The underlying idea behind multi-bit flip-flop method is to eliminate the total inverter number by sharing the inverters in the flip-flops. To deal with the difficulty efficiently, we have proposed several techniques. First, we perform a co-ordinate transformation to identify those flip-flops that can be merged and their legal regions. Besides, we show how to build a combination table to enumerate possible combinations of flip-flops provided by a library. Finally, we use a hierarchical way to merge flip-flops. The time complexity of our algorithm is (n1.12) less than the empirical complexity of (n2).Our algorithm significantly reduces clock power by 20–30% and the running time is very short. In the largest test case, which contains 1 700 000 flip-flops, our algorithm only takes about 5 min to replace flip-flops and the power reduction can achieve 21%.
- Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, and Soon-Jyh Chang, Member, IEEE“ Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops,” IEEE transactions on very large scale integration (VLSI) systems, vol. 21, no. 4, april 2013
- P. Gronowski, W. J. Bowhill, R. P. Preston, M. K. Gowan, and R. L.Allmon, “High-performance microprocessor design,” IEEE J. Solid-StateCircuits, vol. 33, no. 5, pp. 676–686, May1998.
- W. Hou, D. Liu, and P.-H. Ho, “Automatic register banking for low power clock trees,” in Proc. Quality Electron. Design, San Jose, CA, Mar. 2009, pp. 647–652.
- D. Duarte, V. Narayanan, and M. J. Irwin, “Impact of technology scaling in the clock power in Proc. IEEE VLSI Comput. Soc. Annu. Symp.,Pittsburgh, PA, Apr. 2002, pp. 52–57.
- H.Kawagachi and T.Sakuari,”a reduced clock-swing flip flop (RCSFF) for 63% clock power reduction ,’in VLSI circuits Dig .Tech.PapersSymp,jun.1997,pp.97-98.
- Y.T .Chang,c,c-.Hsu,P.-H.Lin,Y.-W.Tsai,and S.F.Chen, “Post –placement power optimization with multi-bit flip flops ,’’in Proc. IEEE/ACM Comput.-Aided Design Int.Conf.,San Jose,CA,NOV.2010, pp.218-223.
- Faraday Technology Corporation[Online].Available :http://www.Faraday-tech.com/index.html
- C.Bron and J.Kerbosch,”Algorithm 457:Finding all cliques of an undirected graph,’’ACMCommun,vol.16,no.9,pp.575-577,1973.
- CAD Contest of Taiwan[online].Available: http://cad_contest.cs.Nctu.eu.tw/cad11